As integrated circuits increase in complexity and decrease in size, the circuits become more susceptible to damage from high voltage transients. Presently, circuits having metal-oxide-semiconductor (MOS) transistors with gate lengths on the order of 0.15 microns or less operate at voltage levels below about 3.0 volts. Circuits having such small feature sizes are vulnerable to dielectric breakdown during high voltage transients. Additionally, many circuits such as memory devices and the like include high speed input/output nodes that require individual high-voltage protection devices. Accordingly, many circuits require multiple high-voltage protection devices. To avoid interfering with circuit operation, it is important that the protection circuit not create high parasitic line capacitance.
Devices for protecting circuits against high-voltage transients such as ESD events include resistors, rectifiers, clamped MOS transistors acting as lateral bipolar devices, and serially or parallel connected diodes. In order to keep fabrication costs low and to maintain a compact circuit layout, high-voltage protection devices are typically fabricated with the same processing steps as those employed to fabricate the functional components of the protected circuit. In particular, various diode configurations have been developed for integration into standard circuit fabrication processes. Typically, diodes are formed by creating p+ and n+ regions in a semiconductor substrate. This particular diode structure is highly compatible with processes used to form complementary-MOS (CMOS) devices. The p-n junction can be created by special ion implantation processes devoted to the creation of the n+ and p+ regions in the substrate, or by taking advantage of the p-n junctions created in the substrate by the p+ and n+ well regions.
Further improvement in the high-voltage protection offered by diode protection circuits can be realized by creating diodes with polysilicon gate structures. The polysilicon gate diode, or poly-bounded diode, is effective in protecting circuits from high-voltage transients and can be fabricated to have low parasitic capacitance. In the poly-bounded diode, a silicon channel region beneath the polysilicon layer separates the n+ region and the p+ region in the substrate. The silicon channel region improves diode ESD performance by dissipating heat and reducing the current density through the diode. Additionally, the silicon channel region functions to lower the parasitic capacitance to levels below that obtainable in diodes lacking a silicon channel region.
While poly-bounded diodes offer an effective means for protecting MOS circuit against high-voltage transients, further improvements are needed to increase the diode performance as circuit dimensions are reduced.